1. Field of the Invention
The present invention relates to a semiconductor memory device and a method of operating the semiconductor memory device.
2. Description of Related Art
In recent years, reduction in chip size and increase in capacity of memories have been advanced. With this, semiconductor memory devices (for example, SRAM) are desired to include high SER (Soft Error Rate) resistance.
Typically, in order to enhance SER resistance, a CR time constant circuit based on capacity and resistance with respect to a memory node (cross-coupled node) of a memory cell of a SRAM is connected, or the capacity of a cross-coupled node itself is increased to increase an accumulated electric charge amount. However, with a method of simply increasing the capacity, the operation speed of a SRAM reduces. In Japanese Patent Laid-Open No. 8-46060, the operation condition at the time of write is improved by setting the potential of a capacitive plate at a low level at the time of write of data (at the time of a storing operation). In other words, in the SRAM adopting a TFT and including a capacitive plate electrode, the influence of the potential of the capacitive plate electrode is relieved.
When a data reading or writing operation is continuously performed for a SRAM, a cross-coupled node continuously repeats the state of H (high) or L (Low), and in such a case, if a subsidiary capacitor is formed in the cross-coupled node, change of the potential level (H or L) becomes slow, and as a result, there arises the problem of reducing the operation speed of the SRAM. In other words, in order to enhance the SER resistance of a SRAM, a capacitor is preferably added to the cross-coupled node, but from the viewpoint of realizing the high-speed operation of the SRAM, it is not preferable to add a capacitor to the cross-coupled node. In Japanese Patent Laid-Open No. 8-46060, consideration is not given to this respect at all.
As described above, with the semiconductor memory device of related art, it is difficult to realize high SER resistance while satisfying the operation speed of the semiconductor memory device.